1. Field of the Invention
The present invention relates to a chip structure and a chip package structure, and more particularly, to a chip structure having a redistribution layer and a stacked-chip package comprising the chip structures.
2. Description of the Related Art
In the contemporary information world, consumers continuously pursue electronic apparatus with higher speed, better quality and more functions. For the product outlook, an electronic apparatus is required to be lighter, thinner, shorter and smaller. In order to achieve this object, the system integration concept has been introduced in the circuit design by the manufacturers, such that one single chip may provide multiple functions and less number of chips is disposed in an electronic apparatus. In addition, for the electronic package technique, in order to adapt with the trend of lighter, thinner, shorter and smaller, various package design concepts such as the multi-chip module (MCM), the chip scale package and the stacked multi-chip package have also been developed.
FIG. 1A is a schematic sectional view of a stacked-chip package comprising multiple chips with an identical or similar chip scale. Referring to FIG. 1A, the conventional stacked-chip package 100 comprises a circuit substrate 110, a chip 120a, a chip 120b, a spacer 130, a plurality of bonding wires 140 and an encapsulant 150. A plurality of bonding pads 112 is disposed on the circuit substrate 110, and a plurality of bonding pads 122a and 122b is disposed on the chips 120a and 102b, respectively. The bonding pads 122a and 122b are disposed on the chips 120a and 120b with peripheral type arrangement. The chip 120a is disposed on the circuit substrate 110, and the chip 120b is disposed over the chip 120a and a spacer 130 is disposed between the chip 120a and the chip 120b. Two ends of some bonding wires 140 are respectively connected to the bonding pads 112 and 122a by a wire bonding process, such that the chip 120a is electrically connected to the circuit substrate 110. In addition, two ends of some other bonding wires 140 are respectively connected to the bonding pads 112 and 122b by the wire bonding process, such that the chip 120b is electrically connected to the circuit substrate 110. Moreover, the encapsulant 150 disposed on the circuit substrate 110 encapsulates the bonding wires 140, the chip 120a and the chip 120b. 
Since the bonding pads 122a and 122b are disposed on the chips 120a and 120b with peripheral type arrangement, the chip 120a cannot directly hold the chip 120b. Therefore, a spacer 130 is disposed between the chip 120a and the chip 120b in the conventional technique, such that an appropriate gap exists between the chip 120a and the chip 120b for performing a subsequent wire bonding process. However, using the spacer 130 inevitably increases the thickness of the conventional stacked-chip package 100.
In order to reduce the thickness of the conventional stacked-chip package, the conventional technique further provides another stacked-chip package comprising multiple chips with a different chip scale as shown in the schematic sectional view of FIG. 1B. Referring to FIG. 1B, the conventional stacked-chip package 100′ comprises a circuit substrate 110, a chip 120c, a chip 120d, a plurality of bonding wires 140 and an encapsulant 150. A plurality of bonding pads 112 is disposed on the circuit substrate 110. Here, the chip 120c is larger than the chip 120d. In addition, a plurality of bonding pads 122c and 122d is disposed on the chips 120c and 120d, respectively. The bonding pads 122c and 122d are disposed on the chips 120c and 120d with peripheral type arrangement. The chip 120c is disposed on the circuit substrate 110, and the chip 120d is disposed on the chip 120c. Two ends of some bonding wires 140 are respectively connected to the bonding pads 112 and 112c by the wire bonding process, such that the chip 120c is electrically connected to the circuit substrate 110. In addition, two ends of some other bonding wires 140 are respectively connected to the bonding pads 112 and 112d by the wire bonding process, such that the chip 120d is electrically connected to the circuit substrate 110. Moreover, the encapsulant 150 disposed on the circuit substrate 110 encapsulates the bonding wires 140, the chip 120c and the chip 120d. 
Since the chip 120d is smaller than the chip 120c, the chip 120d does not cover the bonding pads 122c on the chip 120c when the chip 120d is disposed on the chip 120c. However, when multiple chips with different scales are stacked to form the stacked-chip package 100′ with the method mentioned above in the conventional technique, since the chip disposed on the higher layer has less scale, there is a limitation of the number of chips to be stacked in the stacked-chip package 100′.